Traditionally scan diagnosis is used to determine the most likely faulty locations and fault types for a given failing device on scan failures. The diagnosis results guide physical failure analysis (PFA) to locate defects and identify the root cause. Defects are typically classified into two categories based on defect locations. A defect in a library cell is called a cell internal defect and a defect on interconnecting wires is called an interconnect defect. Significant progress has been made in the area of interconnect defect diagnosis. Various fault models are developed to address different fault effects and layout information is incorporated into the diagnosis process. The improved diagnosis accuracy and resolution enable failure analysis engineers to focus on smaller areas, reduce the turnaround time and cost, and improve the PFA success rate. Scan diagnosis has also been applied directly to yield analysis. Volume diagnosis results are analyzed to identify systematic yield limiters.
Efforts have also been made to provide better accuracy and resolution for cell internal defects. In one approach, a transistor-level defect is first mapped into a gate-level defect, and then a conventional gate-level diagnosis tool is applied to the converted gate-level design to identify faulty gates and pinpoint faulty transistors. Another approach is based on excitation condition extraction. Defective cells are first determined by conventional gate-level diagnosis techniques. Then the failing excitation conditions and passing excitation conditions for interested cells are extracted from the test patterns. The failing excitation conditions are the logic value combinations on the inputs of the defective cell that can activate the internal defects and propagate the effects to the cell outputs. The passing excitation conditions are the logic value combinations on the inputs that cannot excite or propagate the internal defect to the cell outputs.
Various techniques have been developed to derive cell internal defect candidates from the extracted excitation condition. In one of such techniques, an excitation condition table for stuck-open faults is correlated with a gate input sequence table to diagnose the cell internal defects with sequence dependent defect behavior. In another one, switch level simulation is first used to create a fault dictionary for cell internal faults, including bridges faults, stuck-at faults and stuck-open faults. Excitation conditions for suspect cells are matched against the pre-generated fault dictionary to come up with the final report.
The excitation condition extraction is, however, a non-trivial task, especially for widely used multi-cycle test patterns. Moreover, while the defective cell may be located, the exact defect location within that cell cannot be determined. Recently, a new cell-aware diagnosis technique based on fault models derived by analog simulation has been developed by the applicant. This new technique can pinpoint the defect location within a cell for various cell internal defects.
Despite the aforementioned developments, conventional diagnosis techniques can still fail to identify some defective cells. In particular, a defective cell can be missed by a conventional diagnosis technique if fault effects do not propagate through the defective cell itself (a sink cell) but through other cells that share the same driver cell with the defective cell (other sink cells) or through all of the sink cells. New fault models and diagnosis processes are needed to address the problem.